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This paper deals with the implementation of low voltage, energy efficient and high speed 1-bit Full Adder (FA) cell in pass transistor (PT) logic by using 20 nm compact model parameters. The existing full adder with pass transistor logic suffers from a drawback of replication of full swing in sum and carry outputs and voltage step existed in both the outputs at low to high transition. These will be...
This paper provides an overview of the power measurement techniques in sensor network localization in which solar charge controlled checks the voltage and current of the battery. This is an ideal low-cost design that could be implemented in many developing countries' the grid energy generators. In this paper, we did work on different frequencies and check the power reduction. It has been observed...
Low Voltage Digitally Controlled Impedance (LVDCI) is an I/O standard available on FPGA. This design is LVDCI IO standard based Energy Efficient Vedic Multiplier Design on FPGA. Selection of IO standard play an important role in power dissipation of design. Therefore, we are going to select the most energy efficient IO standards in LVDCI family for Vedic Multiplier. This Vedic multiplier design is...
In this paper we are presenting result of simulation based energy efficient bi-directional visitor counting machine (VCM) on FPGA (Field Programmable Gate Array). In this work, we have used Xilinx software. We have used different IOs standards that include HSTL_I, HSTL_II, HSTL_I_18, HSTL_II_18, LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33. For these IOs standard we have collected the total...
We report experimental results of bit-error-rate (BER) measurements in small-critical-current or lowered-biasvoltage rapid single-flux-quantum (RSFQ) circuits for power reduction. In such reduced-power RSFQ circuits, the BERs can be increased because of the reduced signal-to-noise ratio. We fabricated 2-bit shift registers using a 2.5-kA/cm2 niobium process, and measured BERs by low-frequency tests...
Energy efficient analog-to-digital converters (ADCs) are needed to accommodate implantable biomedical application. This paper presents a high energy efficiency successive approximation ADC with fully differential architecture. In order to improve the energy efficiency, the circuit works at 1-V supply voltage and adopts the self-timed logic to ease the power consumption of the comparator. Simulation...
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